1. Field of the Invention
The present invention relates to an electrically writable and erasable nonvolatile semiconductor memory and a method for manufacturing the same, a rapidly writable and readable volatile semiconductor memory and a method for manufacturing the same, and a semiconductor memory in which a nonvolatile semiconductor memory and a volatile semiconductor memory are mixed on the same chip and a method for manufacturing the semiconductor memory.
2. Description of the Related Art
In a conventional nonvolatile memory such as EEPROM (Electrically Erasable and Programmable Read Only Memory) and the like, an information corresponding to one bit is stored in one cell by attaining two thresholds in one cell. On the contrary, in order to make a memory density higher, a technique in which four or more thresholds are assigned to one cell to then store an information corresponding to two or more bits in the one cell is proposed (M. Bauer et al., ISSCC95, p.132). However, the achievement of this technique requires the accurate control of a threshold voltage, the accurate detection of a minute change of a threshold voltage, and the reliability of charge maintenance which is more excellent than that of the conventional technique. Thus, in this technique, it is actually impossible to always obtain the performance equal to that of the conventional technique. Also, this technique has a problem that a manufacture yield is poor. For this reason, a cell structure in which charges are trapped in a plurality of positions that are physically different from each other to then store an information corresponding to a plurality of bits is newly proposed. (B. Eitan et al, IEDM96, p169, FIG. 6). Also, as the similar cell structure, a structure in which a charge trapping layer is formed on a side wall of a gate electrode is proposed by this inventor (U.S. Patent Publication No. 4881108). However, they have problems that the steps of manufacturing those cell structures are very complex and that the control of channel area is not sufficient.
On the other hand, a request of a recent system-on-chip increases a need that an electrically writable and erasable nonvolatile memory and a rapidly writable and readable volatile memory are formed on the same chip. Especially, a request of VLSI is suddenly increased in which a nonvolatile memory having a floating gate structure, such as the EEPROM, a flash memory and the like, and a rapidly operable dynamic RAM are mixed. However, a memory cell of a recent dynamic RAM has a three-dimension structure, which is very complex, such as a trench structure or a stack structure. For this reason, if the floating gate type nonvolatile memory and the dynamic RAM are mixed, the difference between their memory cell structures causes the manufacturing process to be complex and also causes the number of mask steps to be larger. Hence, the manufacturing cost of the mix chip becomes very expensive.
If the memory cell structure of the floating gate type nonvolatile memory is used to attain the memory cell of the dynamic RAM, the commonness with regard to the cell structures enables the manufacturing process to be simplified, which accordingly enables the drop of the manufacturing cost. However, it is difficult that the common memory cell attains the rapidly writing operation which is the feature of the dynamic RAM.
The present invention is proposed in view of the above mentioned circumstances. It is therefore an object of the present invention to provide a structure of a nonvolatile semiconductor memory which can store an information corresponding to a plurality of bits in a simple cell structure.
Another object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory to manufacture a nonvolatile semiconductor memory for storing an information corresponding to a plurality of bits in a simple cell structure.
Still another object of the present invention is to provide a structure of a semiconductor memory in which an electrically writable and erasable nonvolatile memory and a rapidly writable and readable volatile memory are mixed, in a simply cell structure.
Still another object of the present invention is to provide a method for manufacturing a semiconductor memory in which an electrically writable and erasable nonvolatile memory and a rapidly writable and readable volatile memory are mixed, in a simply manufacturing process.
From the viewpoints of the above-mentioned objects, the first feature of the present invention lies in a nonvolatile semiconductor memory which at least comprises a first gate electrode formed on a main surface of a semiconductor substrate through a gate insulation film, a charge trapping layer formed on a side of the first gate electrode, a second gate electrode formed on the side of the first gate electrode through the charge trapping layer, and a conductive layer through which the first gate electrode and the second gate electrode are electrically connected.
The second feature of the present invention lies in a nonvolatile semiconductor memory which at least comprises a gate insulation film which is formed on a main surface of a semiconductor substrate and made of first, second and third insulation films, a charge trapping layer formed on an end of the second insulation film, and a gate electrode formed on the gate insulation film.
The third feature of the present invention lies in a semiconductor memory in which a nonvolatile semiconductor memory and a volatile semiconductor memory are mixed. Then, the nonvolatile semiconductor memory at least contains a first lower insulation film formed on a main surface of a semiconductor substrate, a first middle insulation film formed on an upper portion of a center in the first lower insulation film, a first charge trapping layer formed on an upper portion of an end of the first lower insulation film, a first upper insulation film formed on upper portions of the first middle insulation film and the first charge trapping layer, and a first gate electrode formed on an upper portion of the first upper insulation film. And, the volatile semiconductor memory at least contains a second lower insulation film which is formed on the main surface of the semiconductor substrate and made of the same material as the first middle insulation film, extremely thin insulation films formed on the main surface of the semiconductor substrate and both ends of the second lower insulation film, a second charge trapping layer which is formed on an upper portion of the extremely thin insulation film and made of the same material as the first charge trapping layer, a second upper insulation film which is formed on upper portions of the second lower insulation film and the second charge trapping layer and made of the same material as the first upper insulation film, and a second gate electrode formed on an upper portion of the second upper insulation film.
The fourth feature of the present invention lies in a semiconductor memory in which a nonvolatile semiconductor memory and a volatile semiconductor memory are mixed. Then, the nonvolatile semiconductor memory at least contains a first lower insulation film formed on a main surface of a semiconductor substrate, a first middle insulation film formed on an upper portion of a center in the first lower insulation film, a first charge trapping layer formed on an upper portion of an end of the first lower insulation film, a first upper insulation film formed on upper portions of the first middle insulation film and the first charge trapping layer, and a first gate electrode formed on an upper portion of the first upper insulation film. And, the volatile semiconductor memory at least contains an extremely thin insulation film formed on the main surface of the semiconductor substrate, a second charge trapping layer which is formed on the extremely thin insulation film and made of the same material as the first charge trapping layer, a second upper insulation film formed on the second charge trapping, and a second gate electrode formed on the second upper insulation film.
The fifth feature of the present invention lies in a nonvolatile semiconductor memory which at least comprises a convex portion or a concave portion formed on a main surface of a semiconductor substrate, a gate insulation film which is formed on the main surface of the semiconductor substrate containing the convex portion or the concave portion and composed of first, second and third insulation films, a charge trapping layer formed on an end of the second insulation film, and a gate electrode formed on the gate insulation film.
The sixth feature of the present invention lies in a nonvolatile semiconductor memory which at least comprises a convex portion or a concave portion formed on a main surface of a semiconductor substrate, a gate insulation film which is formed on the main surface of the semiconductor substrate containing the convex portion or the concave portion and composed of first and second insulation films, a charge trapping layer formed between the first and second insulation films, and a gate electrode formed on the gate insulation film.
The seventh feature of the present invention lies in a nonvolatile semiconductor memory which at least comprises a gate electrode formed on a main surface of a semiconductor substrate through a gate insulation film, a concave portion formed on an end of the gate electrode, and a charge trapping layer formed in the concave portion through an insulation film, wherein the charge trapping layers are formed on both upper portions in a channel area and a source drain area.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.